1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a sub word driver circuit used for a semiconductor memory device having a hierarchy word structure.
2. Description of the Related Art
In a DRAM (dynamic random access memory) field as an example of a semiconductor memory device, increase of a memory capacity and finer processing go ahead every year and the circuit structure becomes complicated. Therefore, a fault is sometimes incorporated in the manufacturing and design processes, but such a fault is screened by a simple test process. It is effective in cost reduction to improve a refreshing characteristic, which is a basic characteristic of the DRAM, through the screening, in addition to the improvement of the whole chip characteristics.
Under such a situation, it has been studied to decrease boron concentration in a memory cell transistor for improvement of the refreshment characteristic. When the boron concentration is decreased, it is possible to suppress leak current due to crystal defects, but a threshold voltage Vth of the memory cell transistor decreases at the same time and the disturbance-resistance characteristic of the memory cell deteriorates. On the other hand, as the technique for increasing the effective threshold voltage Vth of the memory cell transistor, a negative word system is proposed in which a non-selected word line is set to a negative voltage (Vkk).
In another viewpoint, the circuit structure of a word driver is improved. One of typical word driver circuits is shown in FIG. 1. Referring to FIG. 1, a NMOS (N-channel MOS transistor) sub word driver has a feature that a layout area is small. However, a CMOS sub word driver is applied in many cases under the consideration of the time shortening a test process such as a long tRAS test through selection of all the word lines. For example, a semiconductor memory device in which the CMOS sub word driver of 2 transistors shown in FIG. 2 is used is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 8-63964).
In the semiconductor memory device of this conventional example, first and second P-type MOSFETs are connected in parallel between a power supply potential Vcc and a first node, and first and second N-type MOSFET are connected in series between the first node and the ground. Third and fourth P-type MOSFETs are connected in parallel between a high potential Vpp and a second node, and a fifth P-type MOSFET and a third N-type MOSFET are connected in series between the high potential Vpp and a negative potential Vw. The gate of the fifth P-type MOSFET and the gate of the third N-type MOSFET are connected to each other, a node between the gates and the second node are connected, and a fourth N-type MOSFET is provided between the first node and the third node. A connection point between the fifth P-type MOSFET and the third N-type MOSFET is connected with the gate of the fourth P-type MOSFET and the word line. The threshold voltage of the third N-type MOSFET is set to be larger than the threshold voltages of the first, second, and fourth N-type MOSFETs. Thus, in the semiconductor memory device of this conventional example, the word line is set to the negative potential in the non-selection of the memory cells of the DRAM. However, in this negative word system, because an MOS transistor with a high threshold voltage Vth is used as the N-type MOSFET selected in the non-selection of the word line, a delay is caused in the non-selection of the word line.
By the way, in the semiconductor memory device, a hierarchy word system is proposed in accompaniment of increase of the memory capacity. In the hierarchy word system, an NMOS is added to surely establish a non-selected state. Thus, the CMOS sub word driver of this type is composed of 3 transistors, compared with the conventional CMOS sub word driver. A semiconductor integrated circuit apparatus in which a negative word system is applied to a hierarchy word structure is proposed to Japanese Laid Open Patent Application (JP-A-Heisei 11-31384).
In the semiconductor integrated circuit apparatus of this conventional example, when the voltage of a sub word line SWL0 is changed from a high voltage VHH in a selected state to the negative voltage VLL, the voltage of the sub word line SWL0 is first changed to the ground voltage VSS. The ground voltage VSS is connected with the outside and has enough charge supply ability. Then, the voltage of the sub word line SWL0 is changed to the negative voltage VLL in the non-selected state during a period that a precharging operation is carried out to complimentary bit lines B0* and Bm*. The charge supply ability in the negative voltage VLL is small. In this way, in the conventional semiconductor integrated circuit device, the sub word line SWL0 is set to the negative voltage VLL at high speed without increase of the charge supply ability of an internal negative voltage generating circuit and the voltage change of the internal negative voltage VLL accompanying the voltage change of the sub word line is restrained.
In this way, a control of the word line to the non-selected state in the conventional sub word driver circuit (SWD) using the negative word system adopts a 2-step discharge system, in which the voltage of the word line is first changed to the ground voltage VSS and then to the negative voltage VLL. The operation of the sub word driver shown in FIG. 3 in the setting of the word line to the non-selected state will be described below with reference to FIGS. 4A to 4R.
(1) An Operation Example in a Word Line Selection (Word Line Signal SWLT0)
It is supposed that a main word line signal MWLB0, a main word line signal MWLT0, and a sub word line signal FXB0 are set to a ground voltage VSS, a negative voltage VKK, and a high voltage VPP, respectively. At this time, the word line signal SWLT0 is selected. As shown in FIG. 4A, first, the voltage of the main word line signal MWLB0 is changed from the high voltage VPP to the ground voltage VSS to turn on a P-type MOSFET (PMOS) Q31. Subsequently, as shown in FIG. 4B, because the main word line signal MWLT0 is in the negative voltage VKK, the NMOS Q32 is kept to the off state. Subsequently, as shown in FIG. 4E, the voltage of the sub word line signal FXB0 is changed from the high voltage VPP to the negative voltage VKK. The sub word line signal FXB0 is supplied to the gate of an N-type MOSFET (NMOS) Q33, which is turned off. Also, as shown in FIG. 4F, the voltage of the sub word signal FXT0 is changed from the ground voltage VSS to the voltage VPP by an inverter in response to the voltage change of the sub word line signal FXB0, and the sub word signal FXT0 is supplied to the source of the PMOS Q31. As shown in FIG. 4M, the voltage of the selected word line PSWLT0 is changed to the voltage VPP through the MOS Q31. At this time, the NMOS Q32 has been turned off in order to keep the main word line signal MWL0 to the negative voltage VKK.
(2) The Operation Example in Case of the Non-Selection of the Word Line (Word Line Signal SWLT0)
When the main word line signal MWLB0, the main word line signal MWL0, and the sub word signal FXB0 respectively change into voltage VPP, VPP and VPP from the word line selection state, and the word line signal SWLT0 is set to the non-selected state. First, as shown in FIG. 4A, the main word line signal MWLB0 changes from the ground voltage VSS to the voltage VPP to turns off PMOS Q31. As shown in FIG. 4B, at substantially the same time, the main word line signal MWL0 changes from the negative voltage VKK to the voltage VPP and the word line FSWLT0 changes to the ground voltage VSS through the NMOS Q32. When the word line goes to the ground voltage VSS sufficiently, the main word line signal MWLT0 changes from the voltage VPP to the negative voltage VKK to turn off the NMOS Q32, as shown in FIG. 4B. In response to this, as shown in FIG. 4E, the sub word signal FXB0 changes from the ground voltage VSS to the voltage VPP. Also, as shown in FIG. 4F, the sub word line signal FXT0 changes from the voltage VPP to the voltage VSS. Because the sub word signal FXB0 is supplied to the gate of the NMOS Q33, the NMOS Q33 is turned on. The word line FSWLT0 changes to the negative voltage VKK through the NMOS Q33 and the word line FSWLT0 is set to the non-selected state.
In the generation of 1 Gbit DDR I/II, the low skew design (the increase of the I/O line width) is necessary because of the increase of the number of the I/O wiring lines and the achievement of the high-speed operation (the data frequency: 667 MHz). Therefore, the width of the I/O wiring line on the memory array must be expanded. Moreover, to reduce noise at the time of the sense operation, the power supply wiring line width on the array must be sufficiently widened.
As described above, when the 2-step discharge method is applied to the negative word method, the main word line signal MWLB and the main word line signal MWLT become necessary, compared with the sub word driver circuit before the negative word method is applied. Thus, the wiring lines which passes on the array become twice. Therefore, the number of wiring lines on the memory array increases and the wiring line width cannot be widened.
In conjunction with the above description, a word driver circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 9-180444). The word driver circuit of this conventional example is provided for a memory circuit in which a first power supply and a second power supply higher than it are supplied. A first transistor of a first conductive type is provided, and a second transistor of a second conductive type is provided to have a gate connected with a gate of the first transistor. In the second transistor, one of source and drain electrodes is connected with one of the source and drain electrodes of the first transistor. The other of the source and drain electrodes of the second transistor is connected with the first power supply. A word line is connected with the source or drain electrodes of the first and second transistors which are connected in common. The gates connected in common are supplied with a first signal having one of a first voltage which is generated by decoding a first address signal group and which is set the second transistor to the conductive state, and a second voltage which is lower than a first power supply. The other of the source and drain of the first transistor is supplied with a second signal having one of a third voltage as the selection state voltage of the word line which is generated by decoding a second address signal group and a fourth voltage which is lower than the first power supply. In this way, in the word driver circuit of this conventional example, the sub word driver circuit is simplified and the number of elements and the number of control signals are reduced.
Also, a semiconductor integrated circuit device is disclosed in the Japanese Laid Open Patent Application (JP-P2000-269459A). In the semiconductor integrated circuit device of this conventional example, many MOS transistors and wiring lines are integrated on a semiconductor substrate. The semiconductor integrated circuit device contains main word lines, a plurality of sub word lines branched from the main word lines, a plurality of bit lines provided to intersect the sub word lines, and a memory cell array which is connected with the sub word lines and the bit lines and contains a plurality of memory cells arranged in a matrix. Also, the semiconductor integrated circuit device contains a sense amplifier row which contains a plurality of sense amplifiers connected with each bit line, a main word line drive signal generating circuit to generate a main word line drive signal, a sub word line drive signal generating circuit to generate a sub word line drive signal, and a sub word line non-signal generating circuit which generates a sub word line non-signal. The sub word line drive section is connected with the main word line drive signal generating circuit, the sub word line drive signal generating circuit and the sub word line non-signal generating circuit. The sub word line drive section contains a plurality of sub word line drive circuits to drive each sub word line in accordance with the main word line drive signal, the sub word line drive signal and the sub word line non-signal. Also, the sub word line drive signal has a state that is a boosted voltage higher than an external power supply voltage, and the sub word line non-signal has a state that is the external power supply voltage or an internal lower voltage lower than the external power supply voltage. According to the semiconductor integrated circuit device of this conventional example, the low power consumption is aimed in the word line selection in the semiconductor integrated circuit such as DRAM of the hierarchy word structure and the high integration of the semiconductor integrated circuit is attempted.
Also, a semiconductor memory device is disclosed in Japanese Laid Open Patent Application (JP-P2001-297583A). The semiconductor memory device of this conventional example is composed of a memory array containing a plurality of memory cells arranged in a matrix of rows and columns, a plurality of word lines respectively provided for the rows, a plurality of bit line pairs respectively provided for the columns, and a row decoder which sets a corresponding one of the word lines to a selection level based on an row address signal to activate the memory cells. Also, the semiconductor memory device of this conventional example is composed of a column decoder which selects either one of the plurality of bit line pairs in accordance with a column address signal, and a read/write circuit which carries out read/write of data from/into the memory cell activated by the row decoder through the bit line pair selected by the column decoder. The row decoder is composed of first to third transistors and a signal generating circuit. The first transistor of a first conductive type has first and second electrodes and an input electrode. The first electrode receives a first binary signal which can take a higher voltage which is higher than a power supply voltage and a negative voltage. The second electrode is connected with the corresponding word line. The input electrode receives a second binary signal which can take the higher voltage and the negative voltage. The second transistor of a second conductive type has first and second electrodes and an input electrode. The first electrode receives the negative voltage, the second electrode is connected with the corresponding word line. The third transistor of the second conductive type has first and second electrodes and an input electrode. The first electrode receives the second signal, the second electrode is connected with the input electrode of the second transistor, and the input electrode receives the power supply voltage. The signal generating circuit respectively sets the first and second signals to the higher voltage and the negative voltage in response to application of a previously allocated row address signal to the corresponding word line to set the corresponding word line to the selection level. Thus, the semiconductor memory device of this conventional example can use a lower power supply voltage, and higher reliability is provided.
Also, a test method of many word lines in a semiconductor memory assembly is disclosed in Japanese Laid Open Patent Application (JP-P2002-63800A). In this test method of this conventional example, a plurality of word lines (WL) are powered up to a high voltage, and the active word lines are powered down to a negative VNWL voltage. Inactive word lines are floated in high resistance in a negative voltage VNWL, before the active word lines are powered down. After the active word lines are powered down, all the word lines are connected with the negative voltage VNWL again. Thus, in the conventional method, the multiple WL wafer test can be implemented quickly without being accompanied by a great expense.